Call for Papers

EMC COMPO 2026

The 15th International Workshop on the Electromagnetic Compatibility of Integrated Circuits

December 7th-10th, 2026
Okayama, Japan

Download the Call for paper flyer

Organization and venue

Welcome to Japan — the land where tradition meets cutting-edge technology! Following the successful edition held at Torino in 2024, the EMC community will gather again at the Okayama Convention Center, Japan, from Dec. 7th to 10th, 2026, to share the latest advances and exchange ideas on research progress and technological developments in the various topics described below. The 15th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC COMPO 2026) is organized by the Institute of Electronics, Information and Communication Engineers (IEICE) and technically co-sponsored by the IEEE EMC Society.

Important Dates

Deadline for paper submission:

May 31, 2026

Notification of acceptance:

Aug. 17, 2026

Final paper submission:

Sep. 25, 2026

Information for authors

Authors are invited to submit original contributions in two column and either one-page format for abstract submission (in proceedings only) or full-length format for paper submission (for IEEE Xplore Publication) through the online submission system. For full-length papers, the suggested length is between 2 and 4 pages. The paper must follow the IEEE two-column A4 format for Conference Proceedings.

Awards

The Best Paper Award will recognize outstanding academic research in IC EMC. The Best Student Award will be given to a full-length paper whose first and presenting author is a student.

Topics

Topics of interest include, but are not limited to, the following:

• Susceptibility to EMI of analog and mixed

signal IPs

• EMC of analog and digital sensors
• EMC of ICs for biomedical applications
• EMC of ICs for wireline communications
• Power electronics EMC/EMI
• EME of core blocks and I/Os
• EMC issues in SoC, SiP, and 3D ICs
• Substrate coupling in smart power ICs
• EMC-aware Design of ICs and Guidelines
• Tools to handle EMC at IC and module level
• SI and PI at IC and PCB level
• Measurement methods for chip level EMC
• EMC Standards and regulations
• Materials for improved EMC of ICs
• Long term electromagnetic robustness of ICs
• Influence of IC EMC on system design

Organizing committee

Makoto Nagata,

Kobe University

Tohlu Matsushima,

Kyushu Institute of Technology

Yoshitaka Toyota,

Okayama University

Yuichi Hayashi,

NAIST

Kengo Iokibe,

Okayama University

Kouji Ichikawa,

Nagoya Institute of Technology

Hiroshi Suenaga,

Panasonic

Koh Watanabe,

NICT

Osami Wada,

Nagoya Institute of Technology

Contact information